Data reusability prediction for data bypassing

Abstract

Cache bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large portions of data are never reused. However, most bypass techniques have relied on ad hoc methods such as counters and tables which cannot tackle the complexity of multicore workloads. In this dissertation, we propose an alternative method to predict cache bypassing using Support Vector Machine (SVM) models. Based on access traces obtained from representative benchmarks running on the Multi2Sim simulator, supervised SVM training was performed in order to obtain a bypass prediction model suitable for LLC in multi-core processors. The SVM outputs bypassing classifiers which are integrated on the simulator to quantify LLC performance improvements. Results show that, with appropriate parameters and kernel functions, SVM is capable of generating bypassing models which improve LLC performance on multicore processors, achieving an average 5.34% hit rate improvement across SPLASH2 benchmark combinations.