IMPLEMENTATION OF 1D TRANSFORM FOR HIGH EFFICIENCY VIDEO CODING ON FPGA

Abstract

This thesis proposes a 1-D transform architecture for the latest video coding standard, the High Efficiency Video Coding (HEVC). The design is described in VHDL, and aimed for Field Programmable Gate Arrays (FPGAs), which are suitable for low volume productions. All transform sizes, which are 4x4, 8x8, 16x16, and 32x32, can be computed by the proposed architecture with equally high throughput. The throughput is high enough to encode 8K(7680 pixels x 4320 pixels) videos at 30 frames/s. The proposed architecture can receive flexible input combinations resulting from a quad-tree partitioning. Using dedicated resources in critical tasks such as multiplications is an important strategy for FPGA designs, so dedicated multipliers in the DSP slices are extensively employed to gain high performance design and save general purpose resources. Hardware of a small size transform is completely reused in a larger size to further save the overall resources. Since the dedicated multipliers are usually expensive resources, a multiplier sharing scheme is invented in this thesis. The total number of dedicated multipliers required is reduced such that the design can be implemented on small size FPGA such as the Spartan3A. A scheme called the configuration encoding scheme is created to efficiently represent 1-D transform input combinations resulting from a quad-tree partitioning, which is the partitioning used to get basic processing units of the transform step in the HEVC. Finally, the HEVC reference software is used to encode a set of standard test sequences, then data of the transform step are recorded and compared with simulation results of the architecture to ensure correctness.