A mimetic evolvable hardware for sequential circuits

Abstract

The thesis proposes an on-line evolvable hardware (EHW), called mimetic EHW. The task is to mimic a sequential circuit by observing its partial input/output sequences. The genetic algorithm (GA) is used to search for the circuit satisfying the input/output sequences collected from the target circuit. The mimetic EHW consists of a custom microprocessor and a fitness evaluator. The microprocessor is particularly designed for an execution of GA. The evaluator acts as coprocessor, accelerating the fitness evaluation which is a bottleneck of GA. The microproces-sor and the evaluator are designed using the Verilog hardware description language (Verilog HDL), then realized on Xilinx XC4010 FPGAs. The result shows that, by using the state-of-the-art FPGA, the microprocessor combined with a parallel of 8 fitness evaluators could perform 36 times faster than the software version running on a conventional computer (PentiumPro With Linux OS).