Design of asynchronous dynamic pipelined floating point arithmetic circuits

Abstract

This thesis proposes an asynchronous dynamic pipeline floating-point arithmetic unit which is compliant with single-precision (32 bits) IEEE 754 standard. It is composed of two main parts: the dynamic pipelined floating-point arithmetic unit and the control unit. The arithmetic unit operates five functions: add/subtract, multiply, negate, absolute, and compare. The operation of each function is split into stages to work as a pipelined arithmetic unit. Moreover, five functions can be combined into one circuit to reduce the circuits size. Then, the dynamic pipelining is considered because it is a type of pipeline that can perform multifunction. The control unit is divided into two main parts: pipeline scheduler and stage controller. The control unit uses the pipeline-scheduling scheme to optimize performance and avoid stage collision. Reservation table, collision matrix, and state diagram this scheme. The proposed control unit can be used as a templateto design the control unit of dynamic asynchronous pipelines. Steps of design method for any dynamic asynchronous pipeline are similar to our work, and control parts designed by STG will be applicable. The simulation result shows that the circuit can operate and calculate floating-point number in IEEE 754 standard correctly without stage collision.